1. Field of the Invention
The present invention relates to a MOS transistor, which comprises a gate insulating film including a high dielectric constant film and a gate electrode comprising polycrystalline silicon.
2. Related Art
In recent years, the utilization of a thin film having high dielectric constant called high-k as a component material for the semiconductor devices is actively investigated. Typical high-k material includes oxides of elements such as Zr, Hf and the like. The use of such type of materials for a gate insulating film of a metal oxide semiconductor field effect transistor (MOSFET) reduces a silicon oxide equivarent thickness of the gate insulating film, even though the thickness of the gate insulating film is increased to a certain level, thereby providing a physically and structurally stable gate insulating film.
Japanese Patent Laid-Open No. JP-A-2003-289,140 discloses a MOSFET employing such high-k material. A N channel MOSFET of a surface-channel type is described in this disclosure. A metal silicate film is employed as a gate insulating film. A gate electrode is composed of N-type polycrystalline silicon.
However, a comprehension is obtained according to the recent study, in which a phenomenon called Fermi level pinning is caused when the gate insulating film is composed of a high-k film and the gate electrode is composed of polycrystalline silicon. (C. Hobbs et. al, entitled “Fermi Level Pinning at the PolySi/Metal Oxide Interface”, 2003 Symposium on VLSI Technology Digest of Technical Papers) It is considered that Fermi level pinning is caused when an energy level is created on the basis of chemical bonding of silicon with the above-described metal composing the high-k film within polycrystalline silicon composing the gate, in vicinity of an interface of the gate insulating film in the gate electrode. The disclosure of this literature also describes that Fermi level pinning is caused when high-k films such as HfO2 or Al2O3 is provided so as to contact polycrystalline silicon.
When Fermi level pinning is caused in gate polycrystalline silicon of the MOSFET, a depletion layer is created in the gate polycrystalline silicon in vicinity of an interface thereof with the gate insulating film. In such condition, sufficient voltage cannot be supplied to the gate insulating film, even though sufficient gate voltage is applied, and thus it is difficult to induce enough amount of carrier in the channel region. As a result, a problem is arisen, in which a threshold voltage is increased, and further a fluctuation in the threshold voltage is also increased. In particular, such phenomenon considerably appears in the P-channel MOS transistor, which comprises the gate electrode including gate polycrystalline silicon that contains P-type impurity.